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flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 1 figure 1: pin assignment (top view) hermetic, multi-chip module (mcm) 32mb, 1m x 32, 3.3volt boot block flash array available via applicable speci cations: ? mil-prf-38534, class h ? dscc smd 5962-09205 features ? 32mb device, total density, organized as 1m x 32 ? bottom boot block (sector) architecture ? operation with single 3.3v supply ? available in multiple access time variations ? individual byte control via individual byte selects (csx\) ? low power cmos ? minimum 1,000,000 program/erase cycles per sector guaranteed ? sector architecture: ? one 16k byte, two 8k byte, one 32k byte and fteen 64kbyte sectors ? any combination of sectors can be concurrently erased ? mcm supports full array (multi-chip) erase ? embedded erase and program algorithms ? erase suspend/resume; supports reading data from or programming data to a sector not being erased ? ttl compatible inputs and outputs ? military and industrial operating temperature ranges option marking access speed 70ns* -70 90ns -90 100ns -100 120ns -120 *contact factory package ceramic quad flat pack q ceramic hex inline pack p temperature range full mil (mil-prf-38534, class h) /q military temp (-55 o c to +125 o c) /xt industrial (-40 o c to +85 o c) /it general description the as8flc1m32b is a 32mb flash multi chip module organized as 1m x 32 bits. the module achieves high speed access, low power consumption and high reliability by employing advanced cmos memory technology. the military grade product is manufactured in compliance to the mil-prf-38534 speci cations, making the as8flc1m32b ideally suited for military or space applica- tions. the module is offered in a 68-lead 0.990 inch square ceramic quad at pack or 66-lead 1.185inch square ceramic hex in-line package (hip). the cqfp package design is tar- geted for those applications, which require low pro le smt packaging. for more products and information please visit our web site at www.micross.com i/o0 i/o1 i/02 i/o5 i/o6 i/o7 gnd i/o10 i/o11 i/o17 i/o18 i/o21 i/o22 i/o23 gnd i/o26 i/o27 i/o16 i/o19 i/o25 i/o20 i/o24 i/o28 i/o30 i/o29 i/o3 i/o9 i/o4 i/o8 10 11 12 13 14 15 16 17 18 09 08 07 06 05 04 03 02 01 68 67 66 65 64 63 62 61 60 59 78 57 76 55 54 53 52 51 50 49 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 i/012 i/o14 i/o13 25 24 23 22 21 19 20 vcc a10 a8 a7 a6 we1\ cs4\ gnd cs3\ a5 a4 a3 a2 a1 a0 a9 reset\ vcc a11 a12 a13 a14 a15 cs1\ oe\ cs2\ a17 we2\ we3\ we4\ a18 a19 nc a16 26 44 i/o15 i/o31 [package designator qt] i/o2 i/o1 i/o0 i/o8 i/o9 i/o10 i/o4 i/o3 i/o5 i/o6 i/o7 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 a0 a18 a11 a16 a14 a15 a9 a10 a17 a8 a7 a4 a5 a6 a1 a2 a3 a12 a13 nc nc cs3\ cs2\ cs1\ cs4\ a19 vcc vcc gnd gnd reset\ oe\ we\ nc 66 hip pin assignment [package designator h] (top view) p
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 2 the device requires only a single 3.3volt power supply for both read and write operations. internally generated and regulated voltages are provided for the program and erase functions. the device is entirely command set compatible with the jedec single power fash standard. com- mands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data required for the programming or erase function(s). reading data out of the array is similar to reading from other electrically programmable devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm that automatically times the write pulse widths and cycle and veri es each cell for proper cell margins. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm, an internal algorithm that automatically pre-programs the array before executing the erase operation. during erasure, the device automatically times the erase pulse widths and veri es proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data\ polling) and dq6 (toggle) status bits. after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from micross. hardware data protection measures include a low vcc detector that automatically inhibits write operations during power transitions. the hardware sector protection features disables both program and erase operation in any combination of the sectors of memory. this can be achieved in-system or via specially adapted commercial programming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector which is not selected for erasure. true background erase can thus be achieved. the hardware reset\ pin terminates any operation in progress and resets the internal state machine to a read operation. the reset\ pin may be tied to the system reset circuitry. logic diagram (byte) 1m x 8 1m x 8 1m x 8 1m x 8 reset\ oe\ a0-ax we1\ we2\ we3\ we4\ cs1\ cs2\ cs3\ cs4\ block diagram i/o0-7 i/o8-15 i/o16-23 i/o24-31 6 8 -ld. cqfp, package "qt" 1m x 8 1m x 8 1m x 8 1m x 8 reset\ oe\ a0-ax we\ cs1\ cs2\ cs3\ cs4\ block diagram i/o0-7 i/o8-15 i/o16-23 i/o24-31 66-ld. hip, package "h" p q gnd vcc reset\ wex\ ry/by\ csx\ x-decoder dq (byte) oe\ a0-ax y-decoder address latch state control command register vcc detector timer pgm voltage generator chip enable output enable logic y-gating cell matrix i/o buffers data latch erase voltage generator sector switches
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 3 a system reset would then also reset the flash device, enabling the system microprocessor to read the boot-up rmware from the flash memory array. the device offers two power-saving features. when addresses have been stable for a speci ed amount of time, the device enters the automatic sleep mode. the system can also place the device into the standby mode. power consumption is greatly reduced in both these modes. device bus operations this section describes the use of the command register for setting and controlling the bus operations. the command register itself does not occupy any addressable memory locations. the register is composed of a series of latches that store the commands, addresses and data information needed to execute the indicated command. the contents of the register serve as the input to the internal state machine. the state machine output dictates the function of the device. table 1 lists the device bus operations, the inputs and control/stimulus levels they require, and the resulting output. the following subsections describe each of these operations in further detail. requirements for reading array data to read array data from the outputs, the system must drive the csx\ and oe\ pins to vil. chip select csx\ is the power and chip select control of the byte or bytes targeted by the system (user). output enable [oe\] is the output control and gates array data to the output pins. write (byte) enables [wex\] should remain at vih levels. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during table 1 the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid data on the device address inputs produce valid data on the data outputs. the device remains enabled for read access until the command register contents are altered. see reading array data for more information. refer to ac read operations table data for timing speci cations relevant to this operational mode. writing commands/command sequences to write a command or command sequence, the system must drive csx\, wex\ to vil and oe\ to vih. an erase command operation can erase one sector, multiple sectors, or the entire array. table 2 indicates the address space contained within each sector within the array. a sector address consists of the address bits required to uniquely select a sector. the ?command de nitions? section has details on erasure of a single, multiple sectors, the entire array or suspending/ resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on each of the data input/output bits within each byte of the mcm flash array. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. icc2 in the dc characteristics table represents that active current specification for the write mode. the ac characteristics section contains timing speci cations for write operations. reset \ cs1 \ cs2 \ cs3 \ cs4 \ we1 \ we2 \ we3 \ we4 \ oe \ operation addresses data bus [dq0-dqx] lhhh d0-d7 out hlhh d8-d15 out hhlh d16-d23 out hhhl d24-d31 out llll d0-d31 out lhhhlhhh d0-d7 in hlhhhlhh d8-d15 in hhlhhhlh d16-d23 in hhhlhhhl d24-d31 in llllllll d0-d31 in vcc+/-0.3v vcc+/-0.3v vcc+/-0.3v vcc+/-0.3v vcc+/-0.3v xxxxx standby x x l l l l hhhhh output disable x l xxxxxxxxx reset x sector address, a6=l, a1=h, a0=l sector address, a6=h, a1=h, a0=l vid xxxxxxxxxtemporary sector un-protect a-in d-in legend l= logic low=vil, h= logic high=vih, vid= 12.0+/-0.5v, x= don't care, ain=address in, dout=data out notes (*) lh vid lllllll llll vid l l l h h h h l h h h read a0-ax in write a0-ax in sector protect sector un-protect d-in, d-out d-in, d-out lh
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 4 table 2 the automatic sleep mode is independent of the csx\, wex\ and oe\ control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. icc5 in the ?dc characteristics table represents the automatic sleep mode current usage. reset\: hardware reset pin the reset\ pin provides a hardware method of resetting the device to reading array data. when the reset\ pin is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset\ pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset\ pulse. when reset\ is held at vss+/-0.3v, the device draws cmos standby current (icc4). if reset\ is held at vil but not within the limits of vcc +/- 0.3v, the mcm array will be in standby, but current limits will be higher than those listed under icc4. the reset\ pin may be tied to the system reset circuitry. a system reset would thus also reset the flash array, enabling the system to read the boot-up rmware code from the boot block area of the memory. sector size secto r a1 9 a1 8 a1 7 a1 6 a1 5 a1 4 a1 3 (kbytes) sa0 000000x 16 sa1 0000010 8 sa2 0000011 8 sa3 00001xx 32 sa 4 0001xxx 64 sa 5 0010xxx 64 sa 6 0011xxx 64 sa7 0100xxx 64 sa8 0101xxx 64 sa9 0110xxx 64 sa10 0111xxx 64 sa11 1000xxx 64 sa12 1001xxx 64 sa1 3 1010xxx 64 sa1 4 1011xxx 64 sa1 5 1100xxx 64 sa1 6 1101xxx 64 sa1 7 1110xxx 64 sa1 8 1111xxx 64 program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on each of the seven data i/o bits within each byte of the mcm flash array. standard read cycle timings and icc read speci cations apply. refer to ?write operation status? for more information, and to ?ac characteristics? for timing speci cations. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode to save on power consumption. the device enters the cmos standby mode when the csx\ and reset\ pins are held at vcc+/-0.3v. if csx\ and reset\ are held at vih, but not within vcc+/-0.3v, the device will be in standby mode but at levels higher than achievable in full cmos standby. the device requires standard access time (tce) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. in the dc characteristics table, icc3 and icc4 represent the standby mode currents. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for tacc + 30ns.
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 5 autoselect code table program or erase operation is not executing, the reset operation is completed within a time of tready. the system can read data trh after the reset\ pin returns to vih. refer to the ?ac characteristics? tables for reset\ parameters. output disable mode when the oe\ input is at vih, output from the device is disabled. the output pins are placed in the high impedance state. autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification through identi er codes output via the appropriate byte dq?s. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment (modi ed to support multi-byte devices, or supplied from the programming equip- ment provider as such), the autoselect mode requires vid (11.5v to bottom boot sector address table 12.5v) on address pin a9. address pins a6, a1, and a0 must be as shown in the autoselect table below. in addtion, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. when all necessary bits have been set as required, the programming equipment may then read the corresponding identi er code on the appropriate byte dq?s. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register. sector protect algorithm flow a19 to a12 to a8 to a5 to description cs1\ cs2\ cs3\ cs4\ oex\ wex\ a13 a10 a9 a7 a6 a2 a1 a0 dqx [output] manufacturers id l hhhl hxxvidxl xl l dq0-7 [01h] xl hhl hxxvidxl xl l dq8-15 [01h] hhl hl hxxvidxl xl l dq16-23 [01h] hhhl l hxxvidxl xl l dq24-31 [01h] device id l hhhl hxxvidxl xl hdq0-7 [5bh] hl hhl hxxvidxl xl hdq8-15 [5bh] hhl hl hxxvidxl xl hdq16-23 [5bh] hhhl l hxxvidxl xl hdq24-31 [5bh] sector protection verificationl hhhl hsaxvidxl xhl dq0-7 [01h] protected hl hhl hsaxvidxl xhl dq8-15 [01h] protected h h l h l h sa x vid x l x h l dq16-23 [01h] protected hhhl l hsaxvidxl xhl dq24-31 [01h] protected l hhhl hsaxvidxl xhl dq0-7 [00h] un -protected hl hhl hsaxvidxl xhl dq8-15 [00h] un- protected h h l h l h sa x vid x l x h l dq16-23 [00h]un-protected hhhl l hsaxvidxl xhl dq24-31 [00h] un -protected sector protect: write 60h to sector address with a7 = 0, a2 = 1, a1 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a7 = 0, a2 = 1, a1 = 0 read from sector address with a7 = 0, a2 = 1, a1 = 0 start plscnt = 1 reset# = v id wait 1 ms first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete ye s ye s no plscnt = 25? ye s device failed increment plscnt temporary sector unprotect mode no no ye s no sector protect algorithm protect another sector? reset plscnt = 1
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 6 sector un-protect algorithm flow sector unprotect: write 60h to sector address with a7 = 1, a2 = 1, a1 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a7 = 1, a2 = 1, a1 = 0 read from sector address with a7 = 1, a2 = 1, a1 = 0 start plscnt = 1 reset# = v id wait 1 ms data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete ye s no plscnt = 1000? ye s device failed increment plscnt temporary sector unprotect mode no all sectors protected? ye s protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address ye s no no ye s no sector unprotect algorithm first write cycle = 60h?
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 7 temporary sector unprotect this feature allows temporary un-protection of previously protected sectors to change data in-system. setting the reset\ pin to vid activates the sector unprotect mode. during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once vid is removed from the reset\ pin, all the previously protected sectors are protected again. the diagram below depicts the algorithm ow for this operation. temporary sector unprotect diagram hardware data protection the command sequence requirements of unlock cycles for programming or erasing provides data protection against inadvertent writes. in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during vcc power-up and power-down transitions, or from system noise. low vcc write inhibit when vcc is less than vlko, the device does not accept any write cycles. this protects data during vcc power-up and power-down. the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than vlko. write pulse ?glitch? protection noise pulses of less than 5ns (typical) on oe\, csx\ or wex\ do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe\=vil, csx\=vih or wex\=vih. to initiate a write cycle, csx\ and wex\ must be a logical zero while oe\ is a logical one. power-up write inhibit if wex\=csx\=vil and oe\=vih during power-up, the device does not accept commands on the rising edge of wex\. the internal state machine is automatically reset to reading array data on power-up. command de nitions writing speci c address and data commands or sequences into the command register initiates device operations. the command register table de nes the valid register command sequences for this device module. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of wex\ or csx\, whichever happens later. all data is latched on the rising edge of wex\ or csx\, whichever happens rst. refer to the ac timing references for correct timings of the appropriate signals. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read data after completing an embedded program or embedded erase operation. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. the system must issue the reset command to re-enable the device for reading array data if dq5, dq13, dq21 and dq29 goes high, or while in the autoselect mode. notes: 1. all protected sectors unprotected 2. all previously protected sectors are protected once again reset\ = vid (note 1) perform erase or program operations reset\ = vih start temporary sector unprotect completed (note 2)
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 8 reset command writing the reset command to the device resets the device to reading array data. address bits are don?t care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, the device ignores reset command requests until the rst initiation of the operation has completed. the reset command may be written between the sequence cycles in a program command sequence and before programming begins. this resets the device to reading array data. once programming begins, the device ignores additional reset command requests until the current operation has completed. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, allowing the user determination as to whether or not a sector is protected. this method is an alternative to device programmers but requires vid on address bit 9 (a9). the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect commamd. the device then enters the autoselect mode, and the system may read at any address, any number of times, without initiating another command. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h returns 01h if that sector is protected, or 00h if it is un-protected. byte program command sequence programming is a four-bus-cycle operation. the program com- mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiates the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and veri es the programmed cell margin. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq31, dq30, dq23, dq22, dq15. dq14, dq7, dq6. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?, this can only be accomplished via an erase operation. unlock bypass command sequence the unlock bypass feature allows the system to program bytes to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by rst writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass command operation is all that is required to program in this mode. the rst cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence. the rst cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care fore both cycles. the device then returns to reading array data. chip erase command sequence chip erase is a six-bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to pre-program prior to erase. the embedded erase algorithm automatically pre- programs and verifies the entire array for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timing during these operations. any commands written to the chip during the embedded erase operation are ignored. note that a hardware reset
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 9 when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq2, dq6, and dq7 of byte 1; dq10, dq14 and dq15 of byte 2; dq18, dq22 and dq23 of byte 3 as well as dq26, dq30 and dq31 of byte 4. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. when the erase command is written during a sector erase operation, the device requires a maximum of 20us to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time- out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. normal read and write timings and command de nitions apply. reading at any address within erase-suspended sectors produces status data on three dq pins within each byte. dq2, dq6, and dq7 of byte 1; dq10, dq14 and dq15 of byte 2; dq18, dq22 and dq23 of byte 3 as well as dq26, dq30 and dq31 of byte 4 to determine if a sector is actively erasing or is erase-suspended. after and erase-suspended program operation is complete, the system can once again read from or write to within non-suspended sectors. the system can determine the status of the program operation using the dq6, 7 bits of byte 1; dq14, 15 of byte 2; dq22, 23 of byte 3 and dq30, 31 of byte 4; just as in the standard program operation. the system may also write the auto select command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within any commands written to the chip during the embedded erase operation are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase operation by using byte data from each of the four bytes. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. sector erase command sequence sector erase is a six-bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and veri es the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50us begins. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50us, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50us, the system need not monitor dq3, dq11, dq19 or dq27 to determine if the sector erase has timed out. the time-out begins from the rising edge of the nal wex\ pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the op- eration. the sector erase command sequence should be reinitiated once
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 10 erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. the system must write the erase resume command to exit the erase suspend mode and continue the sector erase operation. further writes of the resume com- mand are ignored. another erase suspend command can be written after the device has resumed erasing. erase operation diagram write operation status the device provides several bits to determine the status of a write operation: dq2, dq3, dq5, dq6 and dq7 of byte 1; dq10, dq11, dq13, dq14 and dq15 of byte 2; dq18, dq19, dq21, dq22 and dq23 of byte 3; as well as, dq26, dq27, dq29, dq30 and dq31 of byte 4. dq7, dq15, dq23 and dq31: data\ polling the data\ polling bit per byte, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data\ polling is valid after the rising edge of the nal wex\ pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 for byte 1, dq15 for byte 2, dq23 for byte 3, and dq31 for byte 4, the complement of the datum programmed to each of these bits. this status also applies to the programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed into each of these status bits. the system must provide the program address to read valid status information. if a program address fails within a protected sector, data\ polling is active for approximately 1us, then the device returns to reading array data. during the embedded erase algorithm, data\ polling produces a ?0? on the data\ polling status bits. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data\ polling produces a ?1? on each of the data\ polling status bits. this is analogous to the complement/true data output described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?compliment?, or ?0?. the system must provide an address within any of the sectors selected for erasure to read valid status information. after an erase command sequence is written, if all s4ctors selected for erasing are protected, data\ polling is active for approximately 100us, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects a data\ polling status bit has changed from the complement to true data, it can read valid data at each of the bytes on the following read cycles. this is because data\ polling algorithm diagram write erase command sequence data poll from system erasure completed start data = ffh? no yes read byte data address = va start dq5, dq13, dq21, dq29=1? no yes dq7, dq15, dq23, dq31= data? no yes read byte data address = va dq7, dq15, dq23, dq31= data? no yes pass fail
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 11 command de nition table bus cycles (notes 2-4) command sequence first second third fourth fifth sixth (note 1) add r data add r data add r data add r data add r data add r data rea d (note 5) 1ra rd reset (note 6) 1 xxx f0 manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 auto- device id, btm. boo t 4 aaa aa 555 55 aaa 90 x02 5b select sector protect verify (sa) 00 (note 7) (note 8) x04 01 progra m 4 a a a aa 555 55 a a a a 0p a pd unlock bypass 3 aaa aa 555 55 aaa 20 unlock b (note 9) 2 xxx a0 pa pd unlock b (note 10) 2 xxx 90 pa 00 chip eras e 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector eras e 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend (note 11 ) 1 xxx b0 erase resume (note 12 ) 1 xxx 30 legend: x = don't care ra = address of the memory location to be read r d = data read from location ra during read operation pa = address of the memory location to be programmed. addresses latched on the falling edge of wex\ or csx\ pulse, whichever occurs later pd = data to be programmed at location pa. data latches on the rising edge of wex\ or csx\ pulses, whichever occurs later sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19-a13 uniquely select any sector notes 8 . the data is 00h for an unprotected sector and 01h for 1. see table 1 for valid bus operations a protected sector. 2 . all values in hexadecimal 9 . the unlock bypass command is required prior to the 3 . except when reading array or autoselect data, all bus unlock bypass program command. cycles are write operations 10 . the unlock bypass reset command is required to 4 . address bits a19-a12 are don't cares for unlock and return to reading array data when the device is in the command cycles unlock bypass mode 5 . no unlock or command cycles required when 11 . the system may read and program in non-erasing reading array data sectors, or enter the autoselect mode, when int the erase 6 . the reset command is required to return to reading suspend mode. the erase suspend command is array data when the device is in the autoselect valid only during a sector erase operation mode, or if dq5, dq13, dq21, dq29 goes high 12 . the erase resume command is valid only during the (while the device is providing status data) erase suspend mode. 7 . the fourth cycle of the autoselect command sequence is a read cycle. cycles 55 aaa 90 4 aaa aa 555 *data is for single byte. byte 1 = dq0 - dq7 byte 2 = dq8 - dq15 byte 3 = dq16 - dq23 byte 4 = dq24 - dq31
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 12 dq7, dq15, dq23 and dq31 may change asynchronously with the 7 lower order bits within each byte, while the oex\ pins are asserted low. dq6, dq14, dq22 and dq30: toggle bit 1 toggle bit 1 indicates whether an embedded program or erase algorithm is in progress, complete, or has entered the erase suspend mode. toggle bit 1 may be read at any address and is valid after the rising edge of the nal wex\ pulse in the command sequence as well as during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles that access any address will cause this status indicator to toggle. when the operation is complete, the status bit will stop toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, the toggle bit(s) will toggle for approximately 100us, then will become steady state as the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm will cause erasure of unprotected sectors, ignoring the selected sectors that are protected. the system can use dq2, dq6 of byte 1; dq10, dq14 of byte 2; dq18, dq22 of byte 3; dq26, dq30 of byte 4 together to determine whether a sector is actively erasing or is erase suspended. when the device is actively erasing the dq6 of byte 1; dq14 of byte 2; dq22 of byte 3 and dq30 of byte 4 toggles and when the devices enters erase suspend, the status bit returns to a steady state. however, the system must also use dq2 of byte 1; dq10 of byte 2, dq18 of byte 3 and dq26 of byte 4 to determine which sectors are erasing or erase suspended in each of the bytes contained in the module. alternatively dq7, dq15, dq23 and dq31 can be used (see dq7, dq15, dq23, dq31 data\ polling). if a program address falls within a protected sector, dq6, 14, 22, and or dq30 will toggle for approximately 1us after the program command sequence is written, then returns to reading array data. dq6, 14, 22, and or dq30 also toggles during the erase suspend program mode, stops toggling once the operation is complete. dq2, dq10, dq18 and dq26: toggle bit ii the ?toggle bit ii? on each of the bytes, when used with dq6, 14, 22, and dq30 indicates whether a particular sector is actively erasing or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the nal wex\ pulse in the command sequence. dq2, 10, 18 and or dq26 toggles when the system reads at addresses within those sectors that have been selected for erasure, but does not indicate when a sector is being erased. dq6, 14, 22 and dq30 by comparison indicates that a device is actively erasing or in erase suspend, but cannot distinguish which sectors are selected for the operation, therefore both status bits are required for sector and mode information. reading toggle bits i/ii whenever the system initially begins reading toggle bit statuses, it must read byte data (ie?dq0-7, dq8-15, dq16-23 and or dq24-31) at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the rst read. after the second read, the system would compare the new value of the toggle bit with the rst. if the toggle bit is not toggling the device has completed the program or erase operation. the system can read array data on each byte during the next read cycle. if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5, 13, 21 and or dq29 is high. if high, the system should then determine again whether the toggle bit(s) are again toggling, since the toggle bit may have indeed stop toggling just as dq5, 13, 21 and or dq29 went high. if the toggle bit is no longer toggling, the device has successfully completed the operation. if the toggle bit is still active (toggling), the device has not successfully completed the operation and the system must write the reset command to return to reading array data.
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 13 the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5, 13, 21, and or dq29 has not gone high. the system may continue to monitor the toggle bit and dq5, 13, 21, and or dq29 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. toggle bit algorithm diagram dq5,13,21,and or dq29: exceeding timing limits dq5, 13, 21, and or dq29 indicates whether the program or erase time has exceeded a speci ed internal pulse count limit. under these conditions this will produce a logic level ?1? high. this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5, 13, 21 and or dq29 failure condition may appear if the system tries to program a ?1? to a location that was previously programmed to a logic level ?0? low. only an erase operation can change a logic level ?0? back to a logic level ?1?. under this condition, the device halts operation and when the operation has exceeded the timing limits, dq5, 13, 21, and or dq29 will produce a logic level ?1?. under both of these conditions, the system must issue the reset command to return to reading array data. dq3, 11, 19, and or dq27: sector erase timer after writing a sector erase command sequence, the system may read this status bit or bits to determine whether or not an erase operation has begun. if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, this status bit or bits changes from a logic level ?0? to ?1?. the system may ignore this status bit if the system can guarantee that the time between additional sector erase command will always be less than 50us. after the sector erase command sequence is written, the system should read the status on dq7, 15, 23 and or dq31 (data\ polling) or dq6, 14, 22, and or dq30 (toggle bit i) to ensure the device has accepted the command sequence. then read dq3, 11, 19 and or dq27, looking for this bit or bits to be a logic level ?1?. if this bit is a logic level ?1?, the internally controlled erase cycle has begun; all further commands are ignored until the erase operation is complete. if this bit is a logic level ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3, 11, 19 and or dq27 prior to and following each subsequent sector erase com- mand. if this bit or bits is a logic level ?1? on the second status check, the last command might not have been accepted. read(#1) byte data from byte1, 2, 3 and or 4 start toggle bit = toggle? no yes read(#2) byte data from byte1, 2, 3 and or 4 dq5, 13, 21 and or dq29 = "1" no yes read(#1) byte data from byte1, 2, 3 and or 4 read(#2) byte data from byte1, 2, 3 and or 4 toggle bit = toggle? operation not complete, write reset command program/ erase complete no yes
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 14 1. minimum dc voltage on any input or input/output pin is C0.5v. during voltage transitions, input or input/output pins may undershoot vss to C2.0v for periods of up to 20ns. 2. minimum dc input/output voltage on pins a9, oe\, and reset\ is-0.5v. during voltage transitions, a9, oe\, and reset\ may undershoot vss to C2.0v for periods of up to 20ns. maximum dc input voltage on pin a9 is +12.5v which may overshoot to 14.0v for periods up to 20ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one (1) second. *stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. test set-up device under test 3.3v cl 6.2k ohm 1n3064 1n3064 1n3064 pin description/assignment table signal name symbol type pin def/package=qt symbol pin def/package=h description address a0, a1, a2. a3, input 8 , 7, 6, 5, a0, a1, a2. a3, 7, 60, 61, 62, 49, 50, address inputs a4, a5, a6, a7 4, 3, 66, 65, a4, a5, a6, a7 51, 37, 41, 17, 16, 6, a 8 , a9, a10, a11 64, 63, 62, 2 8 ,a 8 , a9, a10, a11 3 8 , 40, 4, 1 8 , 5, 2 8 , a12,a13,a14,a15 29,30,31,32, a12,a13,a14,a15 8 , 21 a16,a17,a1 8 ,a19 33,37,41,42 a16,a17,a1 8 ,a19 chip selects cs1\, cs2 \ input 34, 36, cs1\, cs2 \ 20, 13, 53, 46 active low true chip selects (enables) cs3\, cs4\ 2, 6 8 cs3\, cs4\ write enables we1\, we2 \ input 67, 3 8 ,we \ 29 active low true write enable(s) we3\, we4 \ 39, 40 output enable oe \ input 35 oe \ 27 active low true output enable (x32) reset reset \ input 9 reset \ 12 active low true reset power supply vcc input 61,27 vcc 19, 45 power for core and i/o ground [core] vss input 1,52,1 8 vss 14, 54 digital gnd data input, output i/o0,i/o1,i/o2 input/ 10,11,12,13,14,15, i/o0,i/o1,i/o2 9, 10, 11, 22, 33, 32, data input, output i/o3,i/o4,i/o5 output 16,17,19,20,21,22, i/o3,i/o4,i/o5 31, 30, 1, 2, 3, 15 i/o6,i/o7,1/o 8 23,24,25,26,60,59, i/o6,i/o7,1/o 8 26, 25, 24, 23, 42, 43 i/o9,i/o10,i/o11 5 8 ,57,56,55,54,53, i/o9,i/o10,i/o11 44, 55, 66, 65, 65, 63 i/o12,i/o13,i/o14 51,50,49,4 8 ,47,46, i/o12,i/o13,i/o14 34, 35, 36, 42, 43, 44, i/o15,i/o16,i/o17 45,44 i/o15,i/o16,i/o17 55, 66, 65, 64, 63, i/o1 8 ,i/o19,i/o20 i/o1 8 ,i/o19,i/o20 34, 35, 4 8 , 59, 5 8 , i/o21,i/o22,i/o23 i/o21,i/o22,i/o23 57, 56 i/o24,i/o25,i/o26 i/o24,i/o25,i/o26 i/o27,i/o2 8 ,i/o29 i/o27,i/o2 8 ,i/o29 i/o30,i/o31 i/o30,i/o31 no connection nc open 43 nc 47, 52, 39 no internal connection absolute maximum ratings* absolute maximum ratings parameter symbol min. max. units voltage on vdd pin (note 1) vcc -0.5 4 v voltage on a9, oe\, -0.5 12.5 v and reset\ (note 2) voltage on input pins vin -0.5 vcc+0.5 v voltage on i/o pins vio -0.5 vddq+0.5 v output short circuit current isc 200 ma (note 3) storage temperature tstg -65 150 c operating temperatures / it -40 85 c [screenin g levels] / xt -55 125 c vcntl test conditions test specifications parameter -70/-90 -100/-120 units output load 1 ttl gate output load capacitance, cl (including jig) input rise and fall times 5ns input pulse levels 0.0-3.0 v input timing measurement reference levels output timing measurement reference levels 1.5 v v 30 100 pf 1.5 test specifications paramete r -70/-90 -100/-120 units output load 1 ttl gate output load capacitance, cl (including jig) input rise and fall times 5ns input pulse levels 0.0-3.0 v input timing measurement reference levels output timing measurement reference levels 1.5 v v 30 100 pf 1.5
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 15 dc electrical characteristics symbol parameter test conditions min max units notes ili input load current vin=vss to vcc, vcc=vcc max +/- 5.0 ua ilit a9 input load current vcc=vcc ma,; a9=12.5v 160.0 ua ilo output leakage current vout=vss to vcc, vcc=vcc max +/-5.0 ua 14mhz 120 ma 1,2 8mhz 70 ma 1,2 vcc standby current during reset vil input low voltage -0.5 0.8 v vih input high voltage 0.7xvcc vcc+0.3 v voltage for autoselect and temporary sector unprotect vol output low voltage iol=4.0ma, vcc=vcc min 0.45 v voh1 ioh=-2.0ma, vcc=vcc min 2.4 voh2 ioh=-100ua, vcc=vcc min vcc-0.4 vlko low vcc lock-out voltage 2.3 2.5 v 4 notes: [1] the icc current listed is typically less than 8ma/mhz, with oe\ at vih [2] maximum icc specifications are tested with vcc=vcc max [3] icc active while embedded program or embedded erase algorithm is in progress [4] automatic sleep mode enables the low power mode when addresses remain stable for tacc + 30ns [5] not 100% tested ua vid 11.5 12.5 v reset\=vcc +/- 0.3v vih=vcc +/- 0.3v, vil=vss +/- 0.3v automatic sleep mode 2,3,5 2 2 2,4 ma ua ua icc2 icc3 icc4 icc5 icc1 ce\=vil, oe\=vih vcc active read current ouput high voltage vcc standby current 140 150 150 150 vcc=3.3v ce\=vil, oe\=vih vcc active write current ce\, reset\=vcc +/- 0.3v v
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 16 read operations notes: 1. not 100% tested t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe reset# t df t sr/w t oh read operations timing jedec std 70 90 100 120 t avav t rc min 70 90 100 120 t avqv t acc ce# = v il oe# = v il max 70 90 100 120 t elqv t ce oe# = vil max 70 90 100 120 t glqv t oe max 30353540 t ehqz t df max t ghqz t df max t sr/w min read min toggle and data# polling min t axqx t oh min speed options unit test setup paramete r t oeh output enable hold time 1 description ns output hold time from addresses, ce# or oe#, whichever occurs first 1 read cycle time 1 address to output delay chip enable to output delay output enable to output delay chip enable to output high z 1 output enable to output high z 1 latency between read and write operations 16 16 20 0 10 0
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 17 erase / program operations program operation timings notes: 1. not 100% tested 2. see erase and programming performance for more information notes 1. pa = program address, pd = program data, d out is the true data at the program address. v cc t vcs oe# we# ce# data addresses t ds t ah t d t wp pd t whwh1 t wc t as t wph 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) t ch pa jedec std 70 90 100 120 t avav t wc 70 90 100 120 t avwl t as t wlax t ah t dvwh t ds 35 40 45 45 t whdx t dh t oes t ghwl t ghwl t elwl t cs t wheh t ch t wlwh t wp t whwl t wph t sr/w ns t whwh1 t whwh1 programming operation 2 byte s t whwh2 t whwh2 sec t vcs min s typ ns 5 0.7 50 45 0 35 min ce# setup time ce# hold time write pulse width high latency between read and write operations sector erase operation 2 address hold time data setup time data hold time vcc setup time 1 paramete r 0 0 write pulse width write cycle time 1 address setup time output enable setup time read recovery time before write (oe# high to we# low) unit 30 20 description 0 speed options 0 0 aaah
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 18 chip / sector erase operation timings oe# ce# addresses we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data notes: 1. sa=sector address (for sector erase), va= valid address for reading status data. back to back read / write cycle timing pa valid in valid in valid out valid out pa pa ra t wc t ah t wp t ds t oh t dh t df t ce t cp t oe t rc t acc t wdh t cph t ghwl t sr/w addresses data we# oe# ce# v cc t vcs 555h aaah for chip erase
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 19 data# polling timings (during embedded algorithms) toggle bit timings (during embedded algorithms) g gg(g g ) note va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read c ycle we# ce# oe# high z t oe high z dq7 dq0Cdq6 ry/by# t bus complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cy cle, and array data read cycle. we# ce# oe# high z t oe dq6/dq2 ry/by# t bus addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 20 note the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing dq2 vs. dq6 jedec std t vidr v id rise and fall time 1 min ns t rsp reset# setup time for temporary sector unprotect min s unit all speed options description 500 4 parameter temporary sector unprotect temporary sector unprotect timing diagram reset# t vidr 12 v 0 or 3 v ce# we# t vidr t r sp program or erase command sequence 0 or 3 v
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 21 note for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih sector protect / unprotect timing diagram alternate ce# controlled erase/program operations jedec std 70 90 100 120 t avav t wc 70 90 100 120 ns t avel t as ns t elax t ah ns t dveh t ds 35 40 45 45 ns t ehdx t dh ns t oes ns t ghel t ghel ns t wlel t ws ns t ehwh t wh ns t eleh t cp ns t ehel t cph ns t sr/w latency between read and write operations ns t whwh1 t whwh1 programming operation 2 byte s t whwh2 t whwh2 sec notes: 1. not 100% tested 2. see erase and programming performance data setup time 35 unit typ paramete r min read recovery time before write (oe# high to we# low) write cycle time 1 address setup time address hold time description speed options 30 20 5 data hold time output enable setup time we# setup time we# hold time ce# pulse width ce# pulse width high sector erase operation 2 0 45 0 0 0.7 0 0 0
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 22 erase and programming performance typ 1 max 2 unit comments 0.7 10 s 14 s 7 210 s chip programming time 3 byte mode 8.4 25 s parameter sector erase time chip erase time byte programming time excludes 00h programming prior to erasure excludes system level overhead 5 notes 1.typical program and erase times assume the following conditions: 25c, 3.0 v vcc, 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2.under worst case conditions of 90c, vcc = 2.7 v, 1,000,000 cycles. 3.the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4.in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h be fore erasure. 5.system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the pro gram command. 6.the device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. hardware reset (reset\) jedec std t ready 20 s t ready 500 max all speed options reset# pin low (during embedded algorithms) to read or write (see note) reset# pin low (not during embedded algorithms) unit test setup paramete r description t ready 500 t rp 500 t rh 50 t rpd 20 s min ns (g g) to read or write (see note) reset# pulse width reset# high time before read (see note) reset# low to standby mode note: not 100% tested
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 23 mechanical drawings micross components [package designator q] d d1 d2 b e b l1 r a2 e detail a detail a package specifications symbol max a a2 b b d d1 d2 e e r l1 dimensions in inches min 0.120 0.140 0.005 0.015 0.010 ref 0.800 bsc 0.050 bsc 0.010 typ 0.013 0.017 0.870 0.890 0.980 0.936 1.000 0.956 0.035 0.045 a
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 24 d 4 x ob1 e e1 package specifications symbol max a a1 a2 ob ob1 ob2 d/e d1/e1 d2 d3 e min 0.210 0.245 0.025 0.035 1.000 bsc 0.600 bsc 0.016 0.020 0.065 0.075 1.170 1.140 1.200 0.145 0.155 dimensions in inches l 0.100 bsc 1.150 0.045 0.055 0.135 0.145 d1 d2 66 x ob 65 x ob2 pin 1: sq. pad e l a a1 micross components [package designator p] e mechanical drawings
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 25 ordering information ceramic quad flat pack speed pkg. micross part numbe r configuration (ns) industrial operating range (-40 0 c to +85 0 c) as8flc1m32bq-70/it* 1mx32, 3.3v,flash bottom boot block 70 cqfp-68 as8flc1m32bq-90/it 1mx32, 3.3v,flash bottom boot block 90 cqfp-68 as8flc1m32bq-100/it 1mx32, 3.3v,flash bottom boot block 100 cqfp-68 as8flc1m32bq-120/it 1mx32, 3.3v,flash bottom boot block 120 cqfp-68 extended operating range (-55 0 c to +125 0 c) as8flc1m32bq-70/xt* 1mx32, 3.3v,flash bottom boot block 70 cqfp-68 as8flc1m32bq-90/x t 1mx32, 3.3v,flash bottom boot block 90 cqfp-68 as8flc1m32bq-100/x t 1mx32, 3.3v,flash bottom boot block 100 cqfp-68 as8flc1m32bq-120/x t 1mx32, 3.3v,flash bottom boot block 120 cqfp-68 mil-prf-38534, class h as8flc1m32bq-70/q* 1mx32, 3.3v,flash bottom boot block 70 cqfp-68 as8flc1m32bq-90/q 1mx32, 3.3v,flash bottom boot block 90 cqfp-68 as8flc1m32bq-100/q 1mx32, 3.3v,flash bottom boot block 100 cqfp-68 as8flc1m32bq-120/q 1mx32, 3.3v,flash bottom boot block 120 cqfp-68 hex inline package speed pkg. micross part numbe r configuration (ns) industrial operating range (-40 0 c to +85 0 c) as8flc1m32bp-70/it* 1mx32, 3.3v,flash bottom boot block 70 hip-66 as8flc1m32bp-90/i t 1mx32, 3.3v,flash bottom boot block 90 hip-66 as8flc1m32bp-100/i t 1mx32, 3.3v,flash bottom boot block 100 hip-66 as8flc1m32bp-120/i t 1mx32, 3.3v,flash bottom boot block 120 hip-66 extended operating range (-55 0 c to +125 0 c) as8flc1m32bp-70/xt * 1mx32, 3.3v,flash bottom boot block 70 hip-66 as8flc1m32bp-90/x t 1mx32, 3.3v,flash bottom boot block 90 hip-66 as8flc1m32bp-100/x t 1mx32, 3.3v,flash bottom boot block 100 hip-66 as8flc1m32bp-120/x t 1mx32, 3.3v,flash bottom boot block 120 hip-66 mil-prf-38534, class h as8flc1m32bp-70/q* 1mx32, 3.3v,flash bottom boot block 70 hip-66 as8flc1m32bp-90/ q 1mx32, 3.3v,flash bottom boot block 90 hip-66 as8flc1m32bp-100/ q 1mx32, 3.3v,flash bottom boot block 100 hip-66 as8flc1m32bp-120/ q 1mx32, 3.3v,flash bottom boot block 120 hip-66 * contact factor y
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 26 micross package designator q micross package designator p micross part number smd part number micross part number smd part number as8flc1m32bqt-70/q 5962-0920504hxa as8flc1m32bp-70/q 5962-0920504hya as8flc1m32bqt-70/q 5962-0920504hxc as8flc1m32bp-70/q 5962-0920504hyc as8flc1m32bqt-90/q 5962-0920503hxa as8flc1m32bp-90/q 5962-0920503hya as8flc1m32bqt-90/q 5962-0920503hxc as8flc1m32bp-90/q 5962-0920503hyc as8flc1m32bqt-100/q 5962-0920502hxa as8flc1m32bp-100/q 5962-0920502hya as8flc1m32bqt-100/q 5962-0920502hxc as8flc1m32bp-100/q 5962-0920502hyc as8flc1m32bqt-120/q 5962-0920501hxa as8flc1m32bp-120/q 5962-0920501hya as8flc1m32bqt-120/q 5962-0920501hxc as8flc1m32bp-120/q 5962-0920501hyc micross to dscc part number cross reference for 5962-09205* * micross part number is for reference only. orders received referencing the smd part number will be processed per the smd.
flash as8flc1m32 as8flc1m32b rev. 3.9 03/10 micross components reserves the right to change products or speci cations without notice. 27 document title 32mb, 1m x 32, 3.3volt boot block flash array revision history rev # history release date status 3.3 updated package information may 2008 release 3.4 changed package from qt to q november 2009 release 3.5 changed package designator from h to p november 2009 release 3.6 updated micross information january 2010 release 3.7 removed all "word" references february 2010 release added dscc smd number for cross reference 3.8 added "contact factory" note for -70 february 2010 release 3.9 change volt from 3.0 to 3.3 march 2010 release

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